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Recent content by dick_freebird

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    Lattice FPGA: issue solved after re-flashing the same binary

    Might be a programming link integrity (BER) problem? Or for a nonvolatile-config device, some issue with programming V, I leading to marginal write quality and maybe then, temperature read marginality?
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    SOT223 with 1.1W dissipation and gap pad to its plastic case top?

    I'd look for ways to drop some of that 18V headroom, which is the head of the snake.
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    TLIN (ADS) equivalent model in CADENCE VIRTUOSO

    There is a basic tline in analogLib. There is also another that wants a model, which I've never used (having none) if you want realism like losses and frequency response.
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    50 ohm 30GHz termination in microstrip ring coupler question

    In my observation the "done thing" is to represent what lies within the physical extent of the device in the model (or subcircuit), and leave modeling the interconnect outside those extents to the responsible engineer. Then the "guts" get a marker layer to prevent double-counting interconnect...
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    2 phase boost control IC, 100kHz, current mode

    So how many phases are people interested in? I've seen 2 and 3 mentioned. I've gone as high as teens in charge pumps. At some point I think it becomes sensible to just make a single, and have the controller do the phasing. Or, perhaps some intermediary, SSI-MSI logic that could produce 2-N...
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    OCEAN script issue

    Probably need to develop a Calculator expression that yields the desired result (your wave expression evidently missed a step or several). The only way I've ever gotten an Ocean script to work (and trivial at that) has been to do the task in a foreground ADE session, save the whole session as...
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    Random clock simulate in cadence

    There was another thread very similar very recently. A question is, "Is random-appearing 'good enough'"? You should be able to "box the outcome" by the so-sparse-you-get-bored and the so-close-you-missed-one points. Don't need to look at the entire floor of the "bathtub", generally. Think...
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    2 phase boost control IC, 100kHz, current mode

    The problem is not in the doing. It's in the business plan. We could talk.
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    gpdk width not adjustable

    Have you associated this device library with the correct techfile? The drool looks like technology stuff (callbacks) is not known.
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    ESD protection for I/O of Shift Registor

    Don't worry about machine model ESD. You are not dealing with a unconnected part sliding down a test handler chute. If you want to worry yourself over threats, the threat is going to be more like some of those newer powered system ESD standards (like your HDMI port driver lives a life of...
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    Logic level FET datasheet doent tell Vgs(th) vs temperature

    If you're using the device then you ought to have a couple handy to measure. What's your care-about "off" current? 1mA? 1uA? Pick one for the experiment. Tie D=G, 10V supply, series resistor that gets you the number for drain current at 25C. Record Vgs(25C). Now hit the oven, take Vgs(125C)...
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    Kick Pulse Generator

    Search for "POR" and "power-on reset" for common approaches. You should consider what the supply turnon event looks like as various "trigger" schemes may have dependencies that defeat it in application. Such as a dV/dt trigger needing a minimum supply slew rate, or a POR which doesn't get...
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    SKYwater130nm PDK Install errors in UBUNUTU 22.04

    I recommend that you follow exactly whatever Skywater has suggested. If you choose your own adventure, you may not get the adventure you chose. If need be, get a laptop and flip it to Linux. Or use your Windows machine to VNC to some server where things are already set up right. I've used...
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    LNA DESIGN AND SIMULATION

    I had to chuckle when I got to the part about wanting to do 4GHz in 130nm CMOS with a 12V supply. Pick any two, maybe. But indeed the whole point of a senior project is that you would study, learn and work on your own. Now a valid way to begin would be to trudge on over to the library...
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    Post-layout Results are not correct

    Perhaps is it a proximity coupling effect, why don't you run the two analog extracted netlists side by side and see what you can see?

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