Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In addition to errors by the examiner, by adding '-' and then telling us it was added to display the bits correctly in columns, the OP also casted doubt on which clock cycle the outputs are desired, present or next. I believe a snippet of the question as presented by the examiner should have...
Thank you FvM. Really good catch. I didn't see that there could be z0=1 at any instance where z1=0. A simple simulation (which I didn't do because I expected it to be done by the OP) would have caught that. I'm following the requirements to implement the system using ROM lookup. I only allowed...
Looking back at the question, considering that the question stipulates that you use a ROM for the combinational part, "RESET[n]=(z1[n] OR z1[n-1])" also has to be implemented in ROM. This would mean that the ROM address will be 5 bits, namely, x[n-2], x[n-1], x[n], z1[n-1] and z[n]. The ROM data...
I didn't present that well enough. So please find the update below.
Update:
z1[n+1]=0 if z1[n]=1 or z1[n-1]=1 else z1[n+1]=Q[n+1], where Q is the output of the J-K flipflop. So the J-K flipflop would have an active-high RESET signal that is derived as RESET[n]=(z1[n] OR z1[n-1]).
If the above...
Hi,
Verify this:
z1[n]=0 if z1[n-1]=1 or z1[n-2]=1 else z1[n]=Q[n], where Q is the output of the J-K flipflop. So the J-K flipflop would have an active-high RESET pin that is derived as RESET[n]=(z1[n-1] OR z1[n-2]). If this is verified correct, then we can proceed to derive what feeds the J...
Yes, there is a detailed theory behind sigma-delta modulators. However, there is a limit to what SQNR can be achieved. One can't just say I want to design for a SQNR of 300 dB (just to mention a number) and proceed to achieve it, no matter how hard the person tries.
The noise is more or less...
Yes, I agree that the sigma-delta modulator applies multiple steps to create a number. With the digital sigma-delta modulator, the signal is upsampled to a higher frequency and then interpolated. Then it is quantized to a much lower bit resolution and sampling frequency by downsampling. With...
I know errors due to differential and integral nonlinearities exist. But I'd like to set those to zero for the purpose of what I am doing.
I think I should have mentioned multi-bit digital sigma-delta modulator instead so that we probably would not have to bother about nonlinearities associated...
If you oversample, that automatically results to additional bits. That is in line with the theory of the day. My aim is to reduce quantisation noise without increasing bit resolution or by even decreasing bit resolution, which is what the sigma-delta modulator does.
1701938298
This informs the...
You are right, because even if it were to be possible to determine quantisation error per sample, it would take an infinite number of bits in the fractional part to completely elimimate it.
1701466116
Please kindly state the major reason why it cannot be determined per sample.
1701466630
I'd...
Hi,
Can quantisation error ever be determined per sample of the quantised signal? Viewing quantisation noise as random noise does not seem to truly solve the problem with quantisation noise.
All responses are welcome , please.
Yes, definitely. A plot is provided in the datasheet for AL value Vs Ampere-turns. You could read the AL value for your Ampere-turns from there. The method of calculating inductance from the AL value is the same.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
